Senior Design Engineer – MMU & TLB

位置:

  • 斯洛伐克布拉迪斯拉發
  • Brno, CZ
  • 內華達州拉斯維加斯

工作領域:

  • RTL
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What You’ll be Doing

  • Implementation, debugging, and optimization of a high-performance MMU/TLB for a state-of-the-art processor

Skills Required

  • Requires 5 to 8 years of experience (bright individuals with lower experience can also apply)
  • Experience or background with memory management units, including look-up engines, TLBs, and control
  • Good understanding of system architecture, and experience with power/performance tradeoffs
  • Design experience with deep submicron technology, specifically low power design techniques
  • Verilog / SystemVerilog / Synthesis / STA / CDC / Lint experience
  • Knowledge of programming and scripting languages a plus

Benefits

  • Competitive salary and benefits package.
  • Opportunities for professional development and advancement.
  • International environment and further career progression.
  • Getting in touch with bleeding edge technology.
  • Flexible working hours
  • Work-life balance.
  • Collaborative and supportive work environment.

If you meet the qualifications and are interested in this opportunity, please submit your resume and cover letter. We look forward to hearing from you!

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