Level: Experienced, Full Time Employee
Responsibilities
- Responsibility for design of high performance and low power data processing chip
- Drive and deliver gate level netlist and placement in line with new computational mechanism
- Micro-architectural definition, writing micro-architecture specifications
- Write high performance / low power RTL, Synthesis and Timing closure
- Floor-planning, place and route, including scripted and hand placement of logic
- Explore and characterize SRAM tradeoffs, and cell sizing optimizations
- Collaborate with the verification team to verify the correctness of your unit
- Work with implementation to achieve timing, area, performance and power goals
- Identify performance bottlenecks and optimize system performance
Qualifications
- Member of core team responsible for the crafting and timely delivery of a specific HW units
- A strong background in computer architecture is highly desirable
- Strong communication and interpersonal skills required to work with our global design team
- Successful track record of mentoring junior engineers and interns a plus
- More than 5 years of experience in high performance semiconductor designs
- Verilog expertise and a deep understanding of ASIC design flow
- Expertise in RTL design, logic synthesis, prototyping, timing analysis, floor-planning
- BS or MS Degree in Electrical Engineering or Computer Science
- The ability to learn new technologies and apply that knowledge quickly
- Proven track record demonstrating the ability to meet project milestones and deadlines
Compensation Range
The base salary range is $150,000 to $300,000. Your salary will be determined based on your experience and specific skillset.
You will also be eligible for equity and benefits.
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關於Tachyum
Tachyum正在通過其最近推出的旗艦產品改變人工智能、高性能計算、公共和私有云數據中心市場。 Prodigy神童是世界上第一款通用處理器,將CPU、GPGPU和TPU的功能統一到一個處理器中,為專業和通用計算提供行業領先的性能、成本和能效。當在超大規模數據中心配置Prodigy神童處理器時,它們使所有人工智能、高性能計算和通用應用程序能夠在一個硬件基礎設施上運行,每年為公司節省數十億美元。