We are looking for a skilled design engineers to architect and oversee interfacing our low-speed interfaces to our high-speed interconnect. These blocks include Boot logic, Serial Interfaces, and debug logic
Responsibilities
- Working with a small team to implement, debug, and verify Prodigy’s internal and external buses
- Building the infrastructure needed to bringup and debug the various components in FPGAs and silicon
- Working with the software team to create and verify drivers and models needed
Qualifications
- Requires 8-15 years of applicable experience (bright individuals with fewer years experience would be considered)
- Experience with integration and debug of APB, AHB, and AXI interconnects
- Development of internal logic analyzers and profilers
- Must have Verilog / SystemVerilog / Synthesis / STA / Lint experience
Compensation Range
The base salary range is $125,000 to $200,000. Your salary will be determined based on your experience and specific skillset.
You will also be eligible for equity and benefits.
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关于Tachyum
Tachyum正在通过其最近推出的旗舰产品改变人工智能、高性能计算、公共和私有云数据中心市场。 Prodigy神童是世界上第一款通用处理器，将CPU、GPGPU和TPU的功能统一到一个处理器中，为专业和通用计算提供行业领先的性能、成本和能效。当在超大规模数据中心配置Prodigy神童处理器时，它们使所有人工智能、高性能计算和通用应用程序能够在一个硬件基础设施上运行，每年为公司节省数十亿美元。