Senior Design Engineer – Memory Subsystem

Pracoviská:

  • Santa Clara, Kalifornia
  • Las Vegas, Nevada

Oblasti:

  • IO Systems
Všetky pozície

What you'll be doing

  • Interface and enhancements of an advanced DRAM control block

Skills required

  • Six to ten years of relevant experience
  • Background in design of DRAM interfaces
  • Logic design experience using Verilog/System Verilog
  • The ability to work with a culturally diverse, physically distributed team

Preferred qualifications

  • Experience with RS and BCH codes
  • Experience with FPGA integration and debug

Apply at