Senior Design Engineer - High Speed Cache (Santa Clara, CA)

    Pracoviská:

    • Santa Clara, Kalifornia

    Oblasti:

    • Hardware
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    Responsibilities

    • Working on high performance L2 Cache unit serving the needs of state-of-the art AI processing elements

    Qualifications

    • Requires 1 to 3 years of experience (will consider bright individuals even with lower experience) and the following skills:
    • Understanding of high speed and low power processor pipeline designs / ASICs / SoCs and multi-core designs
    • Strong understanding of computer architecture
    • Experience with cache controller designs, understanding of cache coherency protocols, cache hierarchy
    • Logic design experience with state of the art deep submicron technologies specifically low power design techniques
    • Verilog / system Verilog / Synthesis / STA (Static timing analysis) / CDC / LINT
    • Knowledge of ARM and x86 and multicore processor designs is a plus
    • Knowledge of programming languages C, scripting (Perl / shell / python / awk) is a plus

    Compensation Range

    The base salary range is $150 000 to $300 000. Your salary will be determined based on your experience and specific skillset.

    You will also be eligible for equity and benefits.

    Apply at

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