Senior Design Engineer – PCIe Interface


  • Братислава, Словакия
  • Лас-Вегас, Невада
  • Brno, CZ


  • Hardware
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  • Working with a small team to implement, debug, and verify a high-performance PCIe interface
  • Build the infrastructure to support PCIe during FPGA emulation and bringup


  • Requires 10 to 15 years of applicable experience (bright individuals with lower experience can also apply)
  • Experience and background with PCIe controller/device design
  • Familiarity with bus traffic analyzers and logic analyzers
  • Familiarity with data eye and BER analysis
  • Verilog / System Verilog / Synthesis / STA / CDC / Lint experience

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