 |
We are creating the future now! |
Tachyum is enabling human brain-scale AI and advancing the entire world to a greener era, by delivering the world’s first Universal Processor. |
Newsletter |
Volume 5, Number 2, June 2025 |
 | |
| |
| |
“ |
 Dr. Radoslav Danilak, CEO of Tachyum, was among representatives of Slovak innovative companies and start-ups accompanying the Slovak President Peter Pellegrini’s delegation in Italy. The delegation visited the region of Friuli Venezia Giulia, where it was part of the ceremonial act of laying a wreath at the memorial plaque in honor of General Milan Rastislav Štefánik, a Slovak national hero and a key figure in the establishment of Czechoslovakia. The second day, the delegation visited Turin, where President Pellegrini opened a startup conference at the LIFTT investment fund area, and the Slovak Honorary Consulate with the inauguration of new honorary consul Stefano Buono.  B2B meetings between Slovak and Saudi companies were a part of the Slovak-Saudi Business Forum, the main highlight of the Business Mission to the Kingdom of Saudi Arabia (KSA). Dr. Radoslav Danilak and Marwan Ajam Oghli presented Tachyum. |
Tachyum Radically Cuts the Cost of DeepSeek by Quantizing it to 2-bits |
Tachyum released a new white paper detailing how it efficiently scales Large Language Model (LLM) training and inference through the Mixture of Experts (MoE) approach. The company’s method is further improved by a DeepSeekMoE architecture with 4-bit FP4 data types for activations quantization and 2-bit Tachyum AI (TAI2) sparse weights quantization.  MoEs can match the performance of dense models using approximately 4 times less computing and memory bandwidth, while only memory capacity needs to be increased by approximately 4 times. It is expected that that ratio will continue to grow. This architecture benefits from Tachyum’s proprietary high-performance memory, eliminating the need for costly high-bandwidth memory (HBM) solutions. Successfully quantizing DeepSeek LLM to 2-bit TAI2 further doubles benefit of DeepSeekMoE LLM compared to other architectures.
“DeepSeek’s approach has shown the potential to make next-generation models 10 times more efficient at today’s costs, avoiding the exponential scaling challenges faced by organizations today. With the Prodigy platform, we’re enabling this kind of breakthrough efficiency for AI applications at global scale.” Dr. Radoslav Danilak |
| Download White Paper |
Tachyum Joins UALink |
to Advance the Future of Data Center AI Connectivity |
Tachyum became a member of Ultra Accelerator Link™ (UALink™), a consortium of industry-leading hyperscalers and AI infrastructure providers, to ensure the Prodigy® Universal Processor is compatible with emerging accelerator ecosystems. UALink is a high-speed accelerator interconnect technology that advances next-generation AI/ML cluster performance. The group’s goal is to define and establish an open, interoperable industry standard for high-performance computing connections in scale-up AI environments that enable AI accelerators to communicate more effectively.
“UALink promises high-bandwidth, low-latency connectivity for accelerators, which aligns with Tachyum’s vision for our Prodigy processor architecture. As a non-proprietary, open specification standard, UALink is expected to be adopted by many players across the entire industry making it ideal for addressing the need for efficient multi-accelerator communications as AI models grow.” Dr. Radoslav Danilak |
Latest Achievements |
Tachyum Demonstrates System Management on Prodigy Universal Processor |
Validating SMM shows that Tachyum’s Prodigy is capable of running in this distinct and isolated processor environment, independently of the operating system and transparently to executive and software applications. SMM uses separate on-chip protected static RAM (SRAM), and is installed by the Unified Extensible Firmware Interface (UEFI).  |
| Read more... |
Tachyum Demonstrates DRAM Failover for Large Scale AI on Prodigy FPGA prototype |
Tachyum’s DRAM Failover is an advanced memory error correction technology that improves the reliability of DRAM and provides a higher level of protection than traditional Error Correction Code (ECC). DRAM Failover can correct multi-bit errors within a single memory chip or across multiple memory chips, allowing continued memory operation in the event of device-level faults in memory. With DRAM Failover, even a whole DRAM chip failure can be tolerated without affecting the system and applications.  |
| Read more... |
We Are Hiring |
|
Tachyum® and Tachyum Prodigy®, TPU® are trademarks of Tachyum Ltd, registered in the United States and other countries. All other brand and product names are trademarks of their respective owners. This document is provided for informational purposes only. All statements regarding Tachyum's future direction and intent are subject to change or withdrawal without notice and represent goals and objectives only. © 2019-2025 Tachyum, Inc. All rights reserved. Tachyum, Inc., 8275 South Eastern Ave, Ste 233, Las Vegas, NV 89123, USA Tachyum s.r.o., Karadžičova 14, 821 08 Bratislava, Slovak Republic, EU
|
