The last time Tachyum publicly shared in-depth technical details on Prodigy, it was during the initial design phase when the company unveiled how Prodigy was going to change the data center forever. Throughout the years since then, there have been various third-party reports that have attempted to provide what they felt was happening with Prodigy – some fairly close and some completely off from what the actual design is.

Tachyum released its Prodigy Architectural Overview White Paper that unveils never-before disclosed characteristics of the system-on-chip (SoC) framework, including device layout, and technical features of the world’s first universal processor. The white paper describes in detail how Prodigy addresses processor performance plateauing to overcome the major challenges facing today’s data centers.

“With the release of our architectural white paper, we are able to clear the air and provide detailed information for the technical public. We’re excited for the opportunity to showcase both what Prodigy is today and what it is capable of becoming in the future.””

Dr. Radoslav Danilak

Among the architectural details released in Tachyum’s white paper are:

• CPU core architecture and pipeline
• Prodigy instruction set architecture (ISA), including technical and market dynamics driving the need for a new ISA
• Innovations that minimize data transmission over slow wires by keeping CPU calculations local to circumvent performance limitations
• Unique “half-chip” design that allows the 128-core device to function as two separate 64-core devices
• Powerful AI subsystem that includes 2 x 1024-bit vector units and a 4096-bit matrix unit per core
• Reference designs for Tachyum’s air-cooled evaluation platform, as well as rack and cabinet designs that support both liquid and air cooling

With our architectural white paper detailing the Prodigy processor, we have received tremendous interest and were asked for more details about our AI features. The white paper examines how the Prodigy processor addresses trends in AI, enabling deep learning workloads that are environmentally friendly by achieving less energy consumption and carbon emissions. The AI training models leveraged are all fully functional, ensuring Prodigy remains on the leading edge of the industry.

Among the features described in the latest Tachyum white paper are AI training techniques that include:

• Quantization Aware Training – used with low-precision data types for training deep neural network models. Prodigy processors allow training the deep neural networks using just 8-bit floating point (FP8) representations for all matrix and tensor computations – weights, activations, errors, and gradients. This leads to dramatic improvements in computational efficiency and energy efficiency without impacting model convergence and accuracy, lessening memory transfer times and enabling the use of fast low-precision computing operations.
• Per-Layer Gradient Scaling - Tachyum employs a per-layer gradient scale instead of a global loss scale for the training of deep networks using FP8.
• Sparsity - Tachyum’s Prodigy processor provides native support for block structure sparsity and super-sparsity. It supports sparse matrix multiplication optimized for compressed neural network models thus reducing memory and computation requirements.
• Results for Image Classification and Instance Segmentation – the company trains a wide range of computer vision models, object detection and instance segmentation models using FP8 format.

Prodigy, the world’s first universal processor, successfully runs Security-Enhanced Linux (SELinux), the security architecture for Linux systems that allows administrators to have more control over who can access a system. This latest success of Tachyum’s software team helps satisfy customer requirements in many of its key markets.

Tachyum has entered the Quality Assurance (QA) phase for hardware and software testing on field-programmable gate array (FPGA) emulation boards for Prodigy. It has performed several billion test cycles to ensure the stability of Prodigy FPGA hardware emulators. Now, at QA stage, it will run trillions if not quadrillions of test cycles to demonstrate reliability before product tape-out. The QA process covers component testing, integration testing, regression testing, and performance testing.