Senior Design Engineer 1

Locations:

  • Santa Clara, CA
  • Las Vegas, NV

Job fields:

  • Design
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What you'll be doing

  • Working on Cache Directory block

Skills required

  • Requires 5 to 8 years of experience and following skills:
  • Strong understanding of computer architecture, specifically symmetric multi- processing and cache coherency protocols
  • Experience with coherent interconnect design
  • Logic design experience with state of the art deep submicron technologies specifically low power design techniques
  • Verilog / system Verilog / Synthesis / STA (Static timing analysis) / CDC / LINT
  • Knowledge of ARM and x86 and multicore processor designs is a plus
  • Knowledge of programming languages C, scripting (Perl / shell / python / awk) is a plus

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