Senior Design Engineer – MMU & TLB (California)

Locations:

  • Santa Clara, CA

Job fields:

  • RTL
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What You’ll be Doing

  • Implementation, debugging, and optimization of a high-performance MMU/TLB for a state-of-the-art processor

Skills Required

  • Requires 5 to 8 years of experience (bright individuals with lower experience can also apply)
  • Experience or background with memory management units, including look-up engines, TLBs, and control
  • Good understanding of system architecture, and experience with power/performance tradeoffs
  • Design experience with deep submicron technology, specifically low power design techniques
  • Verilog / SystemVerilog / Synthesis / STA / CDC / Lint experience
  • Knowledge of programming and scripting languages a plus

Compensation Range

The base salary range is $150,000 to $300,000. Your salary will be determined based on your experience and specific skillset.

You will also be eligible for equity and benefits.

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