Senior Design Engineer – Memory Subsystem (California)


  • Santa Clara, CA

Job fields:

  • RTL
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What You’ll be Doing

  • Interface and enhancements of an advanced DRAM control block

Preferred Qualifications

  • Experience with RS and BCH codes
  • Experience with FPGA integration and debug

Skills required

  • Six to ten years of relevant experience
  • Background in design of DRAM interfaces
  • Logic design experience using Verilog/System Verilog
  • The ability to work with a culturally diverse, physically distributed team

Compensation Range

The base salary range is $150,000 to $300,000. Your salary will be determined based on your experience and specific skillset.

You will also be eligible for equity and benefits.

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