Senior Design Engineer – Coherent Interconnect (California)


  • Santa Clara, CA

Job fields:

  • Systems Engineering
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What You’ll be Doing

  • Working with a small team to implement, debug, and verify Prodigy’s high-speed chip-to-chip interface
  • Building the infrastructure to support bringup and debug in FPGAs and silicon
  • Working with the SW team to model and optimize system performance

Skills Required

  • Requires 10 to 15 years of applicable experience (bright individuals with lower experience can also apply)
  • Experience with shared-memory and NUMA
  • Experience with high-speed interconnect
  • System performance modelling experience a plus
  • Verilog / System Verilog / Synthesis / STA / CDC / Lint experience

Compensation Range

The base salary range is $130,000 to $280,000. Your salary will be determined based on your experience and specific skillset.

You will also be eligible for equity and benefits.

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