Senior Design Architect - Interface (California)


  • Santa Clara, CA

Job fields:

  • RTL
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What You’ll be Doing

  • Specify, design, and deliver a high-speed chip-to-chip interface

Preferred Qualifications

  • Experience with high-speed ethernet protocols
  • Experience with coherent interconnect
  • Implementation, emulation, and evaluation experience with FPGAs
  • An advanced degree with research in an applicable field

Skills required

  • MS plus 8 to 12 years of relevant experience
  • Strong understanding of communications protocols
  • Logic design experience using Verilog/System Verilog
  • The ability to write clear specifications and presentations
  • The ability to work with a culturally diverse, physically distributed team

Compensation Range

The base salary range is $150,000 to $300,000. Your salary will be determined based on your experience and specific skillset.

You will also be eligible for equity and benefits.

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