Principal Design Engineer - Coherence

Locations:

  • Santa Clara, CA
  • Las Vegas, NV
  • Bratislava, Slovakia

Job fields:

  • IO Systems
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What you'll be doing

  • Design and deliver state-of-the-art coherency management block

Skills required

  • BS plus 8 to 12 years of relevant experience
  • Strong understanding of CC-NUMA architecture and cache coherence protocols
  • Logic design experience using Verilog/System Verilog
  • The ability to work with a culturally diverse, physically distributed team

Preferred qualifications

  • Experience with system modelling, including performance and efficiency tradeoffs
  • Familiarity with CPU caches and cache hierarchies
  • An advanced degree in an applicable field

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