Design Verification Engineer

Locations:

  • Bratislava, Slovakia

Job fields:

  • Design
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Our team is looking for Design Verification engineers with hands-on experience in multiple projects with verification using UVM based methodology. Candidates must be able to work and integrate third party verification IP and be able to work with protocols like PCIe, Ethernet, DDR4 etc.

Basic qualifications

  • Bachelors or Masters in Electrical or Computer Science
  • 6-8 years of relevant verification experience in UVM
  • Ability to adapt to a start-up fast paced dynamic environment

Skills required

  • Hands on experience with development of System Verilog/UVM based verification environments from scratch.
  • Experience with coverage driven verification methodologies using UVM.
  • Experience with creating/executing test plans, coverage plans leading to successful tapeout.
  • Good understanding of Processor architecture, Pipelines, Caches.
  • Experience working on microprocessors, GPUs or other complex architectures.
  • Ability to write assertions, cover properties, cover points.
  • Knowledge of standard protocols like PCIe and DDR4/5 a plus.
  • Ability to generate functional coverage, code coverage data and going through it with designers, driving the effort of closing the coverage holes and/or resolving them to closure with designers.

Preferred qualifications

  • Bachelors or Masters in Electrical or Computer Science
  • 6-8 years of relevant verification experience in UVM
  • Ability to adapt to a start-up fast paced dynamic environment

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