Design Verification Engineer 2

Locations:

  • Santa Clara, CA
  • Las Vegas, NV

Job fields:

  • Design
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Our team is looking for Design Verification engineers with hands-on experience in multiple projects with development of System Verilog/UVM based verification environments from scratch.

Basic qualifications

  • Bachelors or Masters in Electrical or Computer Science
  • 6-8 years of relevant verification experience in UVM
  • Ability to adapt to a start-up fast paced dynamic environment

Skills required

  • Hands on experience with development of System Verilog/UVM based verification environments from scratch.
  • Experience with coverage driven verification methodologies using UVM.
  • Experience with creating/executing test plans, coverage plans leading to successful tapeout.
  • Good understanding of Processor architecture, Pipelines, Caches.
  • Experience working on microprocessors, GPUs or other complex architectures.
  • Ability to write assertions, cover properties, cover points.

Preferred qualifications

  • Bachelors or Masters in Electrical or Computer Science
  • 6-8 years of relevant verification experience in UVM
  • Ability to adapt to a start-up fast paced dynamic environment

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