Senior Design Engineer – Memory Subsystem


  • Bratislava, Slovakia
  • Brno, CZ

Job fields:

  • Hardware
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  • Interface and enhancements of an advanced DRAM control block


  • Experience with RS and BCH codes
  • Experience with FPGA integration and debug
  • Six to ten years of relevant experience
  • Background in design of DRAM interfaces
  • Logic design experience using Verilog/System Verilog
  • The ability to work with a culturally diverse, physically distributed team


  • Competitive salary and benefits package.
  • Opportunities for professional development and advancement.
  • International environment and further career progression.
  • Getting in touch with bleeding edge technology.
  • Flexible working hours
  • Work-life balance.
  • Collaborative and supportive work environment.

If you meet the qualifications and are interested in this opportunity, please submit your resume and cover letter. We look forward to hearing from you!

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