We are looking for a few high-talent contributors to add to the Tachyum team. Please, take a look at our currently available career opportunities below. You can read the full job description and submit your resume by filling out the form at the bottom.
We’d love to hear from you!
lieux de travail
Champs des Offres d'emploi
lieux de travail | détails | ||
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Senior Linux EngineerBe responsible for designing and maintaining our existing and new Linux infrastructure | IT |
| plus d'information |
Compiler EngineerPort and maintain compilers (GCC, LLVM, Go) on new platform with new computational mechanism | Logiciel |
| plus d'information |
OS Kernel EngineerDesign, develop, port, maintain, test, debug, optimize, secure, and evaluate OS Kernel and system software | Logiciel |
| plus d'information |
Senior Design Engineer – Coherent InterconnectBuild the infrastructure to support bringup and debug in FPGAs and silicon | Systems Engineering |
| plus d'information |
Senior Design Engineer – Coherent Interconnect (California)Build the infrastructure to support bringup and debug in FPGAs and silicon | Systems Engineering |
| plus d'information |
Senior Design Engineer – PCIe InterfaceBuild the infrastructure to support PCIe during FPGA emulation and bringup | Systems Engineering |
| plus d'information |
Java JIT Compiler EngineerPort Java Virtual Machine to new architecture | Logiciel |
| plus d'information |
Student Software DeveloperCreate C/C++, Assembler programs to validate compiler capabilities and effectiveness | Logiciel |
| plus d'information |
AI and Machine Learning Algorithms Architect / ResearcherAnalyze algorithmic and architecture options to find the optimal design points | IA |
| plus d'information |
AI and Machine Learning Algorithms Architect / Researcher (California)Analyze algorithmic and architecture options to find the optimal design points | IA |
| plus d'information |
BMC SW engineer | Logiciel |
| plus d'information |
Build and Release Engineer (Linux)Oversee and ensure build and release timeline. | DevOps |
| plus d'information |
CPU Performance EngineerContribute to architectural planning and design with development engineers | Physical Design |
| plus d'information |
Design Verification EngineersWe are looking for talented Verification Engineers to expand our International Design Verification team. | Design Verification |
| plus d'information |
Design Verification Engineers (California)We are looking for talented Verification Engineers to expand our International Design Verification team. | Design Verification |
| plus d'information |
Digital Design EngineerWork on the state-of-art AI processor architecture. | Physical Design |
| plus d'information |
Linux Kernel EngineerDrive and deliver Linux on new platform with new proprietary computational mechanism | Logiciel |
| plus d'information |
Linux Kernel Networking Specialist (drivers)Create, adjust and maintain various specific network Linux Kernel drivers. | Logiciel |
| plus d'information |
LLVM Compiler EngineerPort LLVM on new platform with new computational mechanism. | Logiciel |
| plus d'information |
Physical Design EngineerWork with RTL designers to achieve PPA goals and suggest appropriate tradeoffs | Physical Design |
| plus d'information |
Physical Design Engineer (California)Work with RTL designers to achieve PPA goals and suggest appropriate tradeoffs | Physical Design |
| plus d'information |
Product Marketing Manager – SlovakiaWork with corporate marketing to provide product and technical information and positioning | Marketing |
| plus d'information |
Senior ASIC Logic & Physical Design EngineerDrive and deliver gate level netlist and placement in line with new computational mechanism | Physical Design |
| plus d'information |
Senior ASIC Logic & Physical Design Engineer (California)Drive and deliver gate level netlist and placement in line with new computational mechanism | Physical Design |
| plus d'information |
Senior Design Engineer - High Speed CacheWork on high performance L2 Cache unit serving the needs of state-of-the art AI processing elements. | RTL |
| plus d'information |
Senior Design Engineer - High Speed Cache (California)Work on high performance L2 Cache unit serving the needs of state-of-the art AI processing elements. | RTL |
| plus d'information |
Senior Design Engineer – CPU Execution UnitWork on Execution Unit. | RTL |
| plus d'information |
Senior Design Engineer – CPU Execution Unit (California)Work on Execution Unit. | RTL |
| plus d'information |
Senior Design Engineer – CPU Fetch UnitWork on state-of-the art Fetch Unit architecture design serving both general purpose as well as AI processing element needs. | RTL |
| plus d'information |
Senior Design Engineer – CPU Fetch Unit (California)Work on state-of-the art Fetch Unit architecture design serving both general purpose as well as AI processing element needs. | RTL |
| plus d'information |
Software EngineerPlay a critical role in porting open source packages to our processor platform, the new chip being designed by Tachyum | Logiciel |
| plus d'information |
Technical Support & Field Application EngineerSupport Tachyum customers and potential customers to easily use and adopt our emulation systems | Logiciel |
| plus d'information |
Toolchain EngineerPlay a critical role in development of debugging tools for the new chip being designed by Tachyum. | Logiciel |
| plus d'information |
UEFI Developer | Logiciel |
| plus d'information |
Senior Design Architect - InterfaceSpecify, design, and deliver a high-speed chip-to-chip interface | RTL |
| plus d'information |
Senior Design Architect - Interface (California)Specify, design, and deliver a high-speed chip-to-chip interface | RTL |
| plus d'information |
Senior Design Engineer – Memory SubsystemInterface and enhancements of an advanced DRAM control block | RTL |
| plus d'information |
Test Engineer / Test Automation EngineerCreate, analyze, and implement software test plans and strategies. | Testing |
| plus d'information |
Junior Linux Kernel developerImplement new or optimize the old features in Linux Kernel. (suitable also for talented graduates) | Logiciel |
| plus d'information |
GCC Compiler EngineerDrive and deliver GCC on new platform with new computational mechanism | Logiciel |
| plus d'information |
GCC Compiler Engineer (California)Drive and deliver GCC on new platform with new computational mechanism | Logiciel |
| plus d'information |
A propos de Tachyum
Tachyum is transforming AI, HPC, public and private cloud data center markets with its recently launched flagship product. Prodigy, the world’s first Universal Processor, unifies the functionality of a CPU, a GPU, and a TPU into a single processor that delivers industry-leading performance, cost, and power efficiency for both specialty and general-purpose computing. When Prodigy processors are provisioned in a hyperscale data center, they enable all AI, HPC, and general-purpose applications to run on one hardware infrastructure, saving companies billions of dollars per year. With data centers currently consuming over 4% of the planet’s electricity, predicted to be 10% by 2030, the ultra-low power Prodigy Universal Processor is critical to continue doubling worldwide data center capacity every four years.
Tachyum, co-founded by Dr. Radoslav Danilak is building the world’s fastest AI supercomputer (128 AI exaflops) in the EU based on Prodigy processors. Tachyum has offices in the United States and Slovakia.