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SAN JOSE, Calif., August 13, 2019 – Tachyum Inc. today announced that it has joined the Peripheral Component Interconnect Special Interest Group (PCI-SIG), a 700+ member association committed to advancing the non-proprietary PCI technology to yield a reliable, scalable solution for high-speed I/O in numerous market applications.
The PCI I/O expansion bus is today’s de facto interconnect between CPUs and peripherals. As demand for higher-performance I/O grows, PCI-SIG’s scope and ecosystem reach expands. Current PCI Express and other related technology roadmaps account for new form factors and lower-power applications. Association members collaborate in open committees to define, test and refine specifications to help companies bring to market PCI-compliant devices.
Innovation in PCIe technology has seen a continued doubling of bandwidth available to graphic cards, hard drives, SSDs, Wi-Fi and Ethernet cards, among others. The fourth-generation of the PCIe standard features bandwidth capabilities of 64GB/s – twice that of the PCIe 3.0 interface. The released PCIe 5.0 specification will double bandwidth rates to 128GB/s. Tachyum is integrating PCIe based on customer needs that will be used for storage, AI, peer-to-peer clusters, and as end-points for accelerator applications.
“Much has been made about the death of Moore’s Law and how the possibility to improve density, power efficiency and cost benefits in the semiconductor industry into the future is problematic,” said Dr. Radoslav Danilak, CEO of Tachyum. “But the advances seen among PCI shows that this simply isn’t true. PCI-SIG has already announced PCIe 6.0, which would double bandwidth again within 3 years. We, at Tachyum, will also ensure that the processor will not be the limiting factor either; it just requires a more innovative approach. We are glad to join the efforts of our fellow members in PCI-SIG in improving the speed capabilities of the next PCIe standard to support the performance needs of data center, AI and Big Data workloads.”
Among other advances to PCIe besides performance improvements, Tachyum is looking for improved support of the memory coherency built into the standard that protocols such as CCIX and CXL bring to multi-core processors to ensure that all copies of data remain coherent. Having this support built into a fully mature and standard architecture ensures that Tachyum’s Prodigy Universal Processor Chip will be able to deliver industry-leading advances in performance, energy consumption, data center server utilization, and space requirements in fully coherent multiprocessor environments utilizing PCIe.
Tachyum’s Prodigy Universal Processor Chip is the smallest and fastest general purpose, 64-core processor developed to date, requiring 10x less processor power, and reducing processor cost by 3x. Prodigy will directly enable a 32-Tensor Exaflop supercomputer and allow the building of machines more powerful than the human brain by 2021, years ahead of industry expectations. Prodigy reduces data center TCO (annual total cost of ownership) by 4x, through its disruptive processor architecture and a smart compiler that has made many parts of the hardware found in typical processors redundant. Fewer transistors, fewer and shorter wires, due to a smaller, simpler core, translates into much greater speed and power efficiency for the Prodigy processor.