Senior Design Engineer – Memory Subsystem

Standorte:

  • Bratislava, Slowakei
  • Brno, CZ

Berufsfelder:

  • Hardware
Zurück zu allen Jobangeboten

Responsibilities

  • Interface and enhancements of an advanced DRAM control block

Qualifications

  • Experience with RS and BCH codes
  • Experience with FPGA integration and debug
  • Six to ten years of relevant experience
  • Background in design of DRAM interfaces
  • Logic design experience using Verilog/System Verilog
  • The ability to work with a culturally diverse, physically distributed team

Bewerben unter

By sending us your application e-mail, you confirm that you have read, understand and accept the content of the Privacy Notice and consent to the processing of your data as part of this application.