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Analyze algorithmic and architecture options to find the optimal design points

Analyze algorithmic and architecture options to find the optimal design points

Develop and implement BMC firmware requirements

Oversee and ensure build and release timeline.

Port and maintain compilers (GCC, LLVM, Go) on new platform with new computational mechanism

Contribute to architectural planning and design with development engineers

We are looking for talented Verification Engineers to expand our International Design Verification team.

We are looking for talented Verification Engineers to expand our International Design Verification team.

Work on the state-of-art AI processor architecture.

Drive and deliver GCC on new platform with new computational mechanism

Drive and deliver GCC on new platform with new computational mechanism

Port Java Virtual Machine to new architecture

Implement new or optimize the old features in Linux Kernel. (suitable also for talented graduates)

Drive and deliver Linux on new platform with new proprietary computational mechanism

Create, adjust and maintain various specific network Linux Kernel drivers.

Port LLVM on new platform with new computational mechanism.

Design, develop, port, maintain, test, debug, optimize, secure, and evaluate OS Kernel and system software

Work with RTL designers to achieve PPA goals and suggest appropriate tradeoffs

Work with RTL designers to achieve PPA goals and suggest appropriate tradeoffs

Work with corporate marketing to provide product and technical information and positioning

Partner with business and engineering leaders to assess the company’s talent requirements and advise on the best hiring strategy in Slovakia, EU and the US

Drive and deliver gate level netlist and placement in line with new computational mechanism

Drive and deliver gate level netlist and placement in line with new computational mechanism

Work on high performance L2 Cache unit serving the needs of state-of-the art AI processing elements.

Work on high performance L2 Cache unit serving the needs of state-of-the art AI processing elements.

Architect and oversee interfacing our low-speed interfaces to our high-speed interconnect

Architect and oversee interfacing our low-speed interfaces to our high-speed interconnect

Build the infrastructure to support bringup and debug in FPGAs and silicon

Build the infrastructure to support bringup and debug in FPGAs and silicon

Work on Execution Unit.

Work on Execution Unit.

Work on state-of-the art Fetch Unit architecture design serving both general purpose as well as AI processing element needs.

Work on state-of-the art Fetch Unit architecture design serving both general purpose as well as AI processing element needs.

Interface and enhancements of an advanced DRAM control block

Build the infrastructure to support PCIe during FPGA emulation and bringup

Build the infrastructure to support PCIe during FPGA emulation and bringup

Be responsible for designing and maintaining our existing and new Linux infrastructure

Play a critical role in porting open source packages to our processor platform, the new chip being designed by Tachyum

Create C/C++, Assembler programs to validate compiler capabilities and effectiveness

Support Tachyum customers and potential customers to easily use and adopt our emulation systems

Create, analyze, and implement software test plans and strategies.

Play a critical role in development of debugging tools for the new chip being designed by Tachyum.

Develop and deliver a UEFI BIOS, including design of new product features