Senior Design Engineer – Memory Subsystem

位置:

  • 斯洛伐克布拉迪斯拉发
  • Brno, CZ

工作领域:

  • 硬件
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Responsibilities

  • Interface and enhancements of an advanced DRAM control block

Qualifications

  • Experience with RS and BCH codes
  • Experience with FPGA integration and debug
  • Six to ten years of relevant experience
  • Background in design of DRAM interfaces
  • Logic design experience using Verilog/System Verilog
  • The ability to work with a culturally diverse, physically distributed team

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