Senior Design Engineer – PCIe Interface

Locations:

  • Bratislava, Slovakia
  • Las Vegas, NV
  • Brno, CZ

Job fields:

  • Hardware
Back to all jobs

Responsibilities

  • Working with a small team to implement, debug, and verify a high-performance PCIe interface
  • Build the infrastructure to support PCIe during FPGA emulation and bringup

Qualifications

  • Requires 10 to 15 years of applicable experience (bright individuals with lower experience can also apply)
  • Experience and background with PCIe controller/device design
  • Familiarity with bus traffic analyzers and logic analyzers
  • Familiarity with data eye and BER analysis
  • Verilog / System Verilog / Synthesis / STA / CDC / Lint experience

Apply at

By sending us your application e-mail, you confirm that you have read, understand and accept the content of the Privacy Notice and consent to the processing of your data as part of this application.